1. Field of the Invention
The present invention relates to techniques for verifying lithographic processes that use photo-masks and semiconductor-manufacturing processes that use write devices.
2. Related Art
Lithography processing represents an essential technology for manufacturing Integrated Circuits (IC) and Micro Electro-Mechanical Systems (MEMS). Lithographic techniques are used to define patterns, geometries, features or shapes. (henceforth referred to as ‘patterns’) onto an integrated circuit die or semiconductor wafer or chips where the patterns are typically defined by a set of contours, lines, boundaries, edges or curves. (henceforth referred to as ‘contours’), which generally surround, enclose, and/or define the boundary of the various regions which constitute a pattern.
Demand for increased density of features on dies and wafers has resulted in the design of circuits with decreasing minimum dimensions. However, due to the wave nature of light, as dimensions approach sizes comparable to the wavelength of the light used in the photolithography process, the resulting wafer patterns deviate from the corresponding photo-mask patterns and are accompanied by unwanted distortions and artifacts.
Techniques such as Optical Proximity Correction (OPC) attempt to improve resolution and/or a process window in a photolithography process by appropriately pre-distorting the photo-mask pattern such that the wafer pattern is printed more accurately. In addition, other techniques known as resolution enhancement technologies (RET) also modify the design of the photo-mask in order to improve photolithography.
A critical issue that arises when using OPC or RET is verifying that an intended photo-mask will print correctly on the wafer, without actually creating the photo-mask (which is an expensive process) or printing wafers in a manufacturing facility or fab (which is also expensive). In addition, there is also a need to determine the robustness of the photo-mask and/or the associated semiconductor-manufacturing process. For example, a manufacturer may be interested in exposure latitude and/or depth of focus (which define a process window). Software is sometimes used to verify suitability of a photo-mask or to estimate the process window by simulating what will actually print on a wafer (henceforth referred to as an estimated wafer pattern).
However, any such verification technique needs a way to determine what errors are acceptable, and what errors constitute a defect. Various methods are used for this purpose today. For example, so-called ‘bridging’ occurs when two features in an estimate of a printed wafer merge. This is generally considered to be a defect. Other approaches include measuring a critical dimension (CD) of a feature at a specific place in an estimated wafer pattern. Unfortunately, these existing approaches may not be systematic. As a consequence, the resulting verification may be incomplete with a negative impact on manufacturing yield and cost.
Hence what is needed are improved systems and methods to facilitate lithography verification.